The present invention is related generally to test methods and structures for integrated circuits. In particular, the present invention is related to clocked based methods and devices for measuring voltage-variable capacitances and other on-chip parameters.
Integrated circuits and their constituent components are tested for a variety of reasons. Completed circuits are tested for functionality and satisfaction of performance parameters. Such performance parameters include circuit speed or frequency of operation and power dissipation. Test cells on a circuit are tested for characterization of device parameters. Such device parameters include insulator dielectric capacitances, junction capacitances and threshold voltages in metal-oxide-semiconductor (MOS) integrated circuits, diode reverse bias leakage currents, dielectric tunneling currents, and, in non-volatile memory devices and standard MOS transistors, the location and density of trapped charges in gate dielectrics. Other circuit parameters are measured as well, such as metal interconnect resistance and interlayer capacitances. In particular, capacitance versus voltage characteristics, C-V curves, are among the most fundamental and popular analysis methods used in the semiconductor industry. These tests are performed during initial process design and characterization and for parametric data gathering even in mature semiconductor manufacturing processes.
Many of these tests require measurement of on-chip capacitances and similar values. Such measurements have grown increasingly unreliable and difficult to make as integrated circuit dimensions have decreased. A capacitance meter has been used, both manually and under automatic control. However, such a meter can be cumbersome, inaccurate and unreliable. For example, current capacitance meters have a resolution of approximately 1 pF. However, many device and interconnect capacitances of interest are in the range of 0.0-100 fF.
Although most on-chip capacitances of interest could be represented in test chip test structures, the large sizes of such structures often prevent their use. Achieving capacitance measurement structures that have enough capacitance to make accurate measurements possible requires that the structures be very large. These large structures consume inordinate amounts of valuable test chip space.
The maximum sizes of test chips are limited by the sizes of the stepping fields of the “wafer steppers” on which the test chips are manufactured. Wafer steppers are the lithographic systems that are currently used in most semiconductor manufacturing facilities for optically patterning the various layers of semiconductor products and of technology development test chips. Steppers use reticules (advanced photolithographic masks) to selectively expose specific areas of photographic emulsions on each wafer during wafer processing. This selective exposure determines the shapes and locations of the polygons that make up the structure of each layer on a semiconductor product or test chip.
Due to each stepper's optical constraints, the area of a wafer or exposure field that a stepper can pattern in a single exposure is limited. Normally, one exposure transfers the pattern from a complete reticule to the photographic emulsion on a wafer. A typical area of a single exposure is 2.5 cm by 2.5 cm. Typically, a single stepper will use a single reticule for patterning a given layer on all of the wafers in a manufacturing wafer lot. Each lot typically consists of 25 or 50 wafers. The stepper starts at one point on each wafer, exposes that location and then steps to the next location and exposes that location. The stepper repeats this process until it has stepped to and exposed all of the assigned locations on a wafer. Hence the term “stepper.”
Different reticules with different patterns are used for different layers. Normally however, only one reticule is used to pattern a single given layer on all of the wafers in a manufacturing wafer lot. Steppers are generally not interrupted in the midst of stepping a wafer lot for the sake of changing to a second reticule. Changing reticules requires that a stepper be disabled for a significant period of time. Any such stepper “down time” is prohibitively costly. The cost of a new semiconductor manufacturing facility's steppers are a major fraction of the cost of the entire facility (on the order of $100 million out of the typical $1 billion that is spent in building and equipping a facility). It would be very impractical, for example, to use one reticule to pattern a layer on a portion of the wafers in a wafer lot and to then to switch to a different reticule to pattern that same layer on the wafers in the remainder of the wafer lot.
Thus the sizes and numbers of test structures that can be placed into a process development test chip are strictly limited to the structures that will fit together into the limited wafer area that is afforded by a single stepper exposure field. While designing the test structures for a test chip, it is common for engineers to make very difficult decisions as to which test structures they will include in the test chip and which test structures they will not include. Omitting structures can often lead to an engineering group later painfully realizing that it does not have the test structures needed answering critical technology development questions. In short, test chip area is extremely costly and reducing the sizes of test structures while maintaining the efficacy of the structures is desirable.
A technique has been developed for measuring on-chip voltage independent capacitance. In “A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement,” McGaughy et al., IEEE Electron Device Letters, Vol. 18, No. 1, January 1997, a technique and circuit are disclosed which permit measuring on-chip capacitances with high resolution. The test structures that the technique uses consume significantly less test chip area than do previous techniques. An on-chip test circuit uses four transistors in addition to the unknown capacitance to be characterized. No reference capacitor is required and resolution down to 0.03 fF is provided. Measurement may be conducted automatically or manually.
While the disclosed technique is useful for measuring voltage independent capacitance, a large class of device and circuit characteristics are voltage dependent or voltage variable. That is, the capacitance of a device or interconnect or other structure varies with applied voltage. Examples include gate capacitance of a MOS transistor or the capacitance of a reverse biased diode. Further, parameters other than capacitance vary with applied voltage and are not measurable with the disclosed technique. These include leakage current in a reverse biased diode and dielectric tunneling currents. All of these voltage variable parameters are key to device characterization and modeling and essential to process control. However, none of these parameters is available using the technique as disclosed in the above-identified reference.
Accordingly, there is a need for an improved method and apparatus for characterizing on-chip devices, currents and capacitances that are variable with applied voltage. Ideally the method will have enough measurement resolution and precision to allow the accurate characterization of capacitors that are small enough to be economically included in technology development test chips.